set_property PACKAGE_PIN AD12 [get_ports i_clk]
set_property IOSTANDARD SSTL135 [get_ports i_clk]
set_property PACKAGE_PIN J12 [get_ports o_cep_en]
set_property IOSTANDARD LVCMOS18 [get_ports o_cep_en]
set_property PACKAGE_PIN H16 [get_ports io_i2c_sda]
set_property IOSTANDARD LVCMOS18 [get_ports io_i2c_sda]
set_property PACKAGE_PIN J16 [get_ports o_i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports o_i2c_scl]

set_property BITSTREAM.GENERAL.COMPRESS true [current_design]





create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_0/inst/clk_out1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {iic_test/u_iic_master/r_bit_cnt[0]} {iic_test/u_iic_master/r_bit_cnt[1]} {iic_test/u_iic_master/r_bit_cnt[2]} {iic_test/u_iic_master/r_bit_cnt[3]} {iic_test/u_iic_master/r_bit_cnt[4]} {iic_test/u_iic_master/r_bit_cnt[5]} {iic_test/u_iic_master/r_bit_cnt[6]} {iic_test/u_iic_master/r_bit_cnt[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {iic_test/u_iic_master/r_i2c_bytedata_shift[0]} {iic_test/u_iic_master/r_i2c_bytedata_shift[1]} {iic_test/u_iic_master/r_i2c_bytedata_shift[2]} {iic_test/u_iic_master/r_i2c_bytedata_shift[3]} {iic_test/u_iic_master/r_i2c_bytedata_shift[4]} {iic_test/u_iic_master/r_i2c_bytedata_shift[5]} {iic_test/u_iic_master/r_i2c_bytedata_shift[6]} {iic_test/u_iic_master/r_i2c_bytedata_shift[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {iic_test/i_rd_data_cnt[0]} {iic_test/i_rd_data_cnt[1]} {iic_test/i_rd_data_cnt[2]} {iic_test/i_rd_data_cnt[3]} {iic_test/i_rd_data_cnt[4]} {iic_test/i_rd_data_cnt[5]} {iic_test/i_rd_data_cnt[6]} {iic_test/i_rd_data_cnt[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {iic_test/i_wr_data_0[0]} {iic_test/i_wr_data_0[1]} {iic_test/i_wr_data_0[2]} {iic_test/i_wr_data_0[3]} {iic_test/i_wr_data_0[4]} {iic_test/i_wr_data_0[5]} {iic_test/i_wr_data_0[6]} {iic_test/i_wr_data_0[7]} {iic_test/i_wr_data_0[8]} {iic_test/i_wr_data_0[9]} {iic_test/i_wr_data_0[10]} {iic_test/i_wr_data_0[11]} {iic_test/i_wr_data_0[12]} {iic_test/i_wr_data_0[13]} {iic_test/i_wr_data_0[14]} {iic_test/i_wr_data_0[15]} {iic_test/i_wr_data_0[16]} {iic_test/i_wr_data_0[17]} {iic_test/i_wr_data_0[18]} {iic_test/i_wr_data_0[19]} {iic_test/i_wr_data_0[20]} {iic_test/i_wr_data_0[21]} {iic_test/i_wr_data_0[22]} {iic_test/i_wr_data_0[23]} {iic_test/i_wr_data_0[24]} {iic_test/i_wr_data_0[25]} {iic_test/i_wr_data_0[26]} {iic_test/i_wr_data_0[27]} {iic_test/i_wr_data_0[28]} {iic_test/i_wr_data_0[29]} {iic_test/i_wr_data_0[30]} {iic_test/i_wr_data_0[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {iic_test/i_wr_data_cnt[0]} {iic_test/i_wr_data_cnt[1]} {iic_test/i_wr_data_cnt[2]} {iic_test/i_wr_data_cnt[3]} {iic_test/i_wr_data_cnt[4]} {iic_test/i_wr_data_cnt[5]} {iic_test/i_wr_data_cnt[6]} {iic_test/i_wr_data_cnt[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 16 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {iic_test/o_rd_data[0]} {iic_test/o_rd_data[1]} {iic_test/o_rd_data[2]} {iic_test/o_rd_data[3]} {iic_test/o_rd_data[4]} {iic_test/o_rd_data[5]} {iic_test/o_rd_data[6]} {iic_test/o_rd_data[7]} {iic_test/o_rd_data[8]} {iic_test/o_rd_data[9]} {iic_test/o_rd_data[10]} {iic_test/o_rd_data[11]} {iic_test/o_rd_data[12]} {iic_test/o_rd_data[13]} {iic_test/o_rd_data[14]} {iic_test/o_rd_data[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 4 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {iic_test/state[0]} {iic_test/state[1]} {iic_test/state[2]} {iic_test/state[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list iic_test/i_i2c_en]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list iic_test/o_i2c_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list iic_test/u_iic_master/r_i2c_sda_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list iic_test/u_iic_master/ro_i2c_scl]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list iic_test/u_iic_master/w_i2c_sda_i]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_100M]
